The hierarchical or "segmented" bit line architecture was developed in recent years in order to increase the integration density of memory chips. This architecture allows for a reduced number of space-consuming sense amplifiers for a given number of memory cells, thus reducing chip size or increasing memory capacity for a given size chip.
In a conventional hierarchical bit line architecture, each column of the memory cell array includes a number of equal length local bit lines (LBLs), directly connected to the memory cells, and a master bit line (MBL) composed of a high conductivity metal disposed at a higher fabrication layer than the local bit lines. For example, each local bit line may connect to several hundred memory cells. Each master bit line is connected directly to a sense amplifier and is selectively coupled to a number of local bit lines in a common column via a number of switches. To access (read, write or refresh) a memory cell connected to a particular local bit line, the switch connecting that local bit line to the master bit line is closed while the other switches in the column are opened.
FIG. 1 illustrates a memory bank 10 of a prior art semiconductor memory utilizing a hierarchical bit line architecture. The memory bank is divided into subarrays of memory cells, e.g., MAa to MAd, and a number of sense amplifier banks such as 12.sub.j, 12.sub.j+1, 12.sub.j+2. In the shown configuration, the sense amplifiers SA.sub.i within each sense amplifier bank are arranged in a shared configuration, such that each sense amplifier amplifies signals from memory cells on both sides thereof in a time multiplexed manner. Each subarray has N columns C.sub.1 -C.sub.N ; however, since the sense amplifiers are shared, each SA bank has N/2 sense amplifiers. Each sense amplifier, e.g., SA.sub.2 of bank 12.sub.j+1 is connected on each side to a master bit line pair consisting of a true master bit line MBL and a complementary master bit line MBL. In this example, each true master bit line MBL is connected to four true local bit lines LBL.sub.1 to LBL.sub.4 of equal length L, and each complementary master bit line MBL is connected to four complementary local bit lines LBL.sub.1 to LBL.sub.4 . The sense amplifier amplifies a differential voltage between the pair of master bit lines--one master bit line is used to carry a reference voltage while the other carries a cell signal transferred thereto by activation of a selected memory cell MC. A word line WL.sub.j in the jth row is activated in accordance with the row address to access the selected memory cell. The configuration shown is known as a folded bit line architecture, wherein the true and complementary bit lines run side by side one another in close proximity. If an open bit line configuration were used, the complementary master bit line would reside on the opposite side of the sense amplifier as the true master bit line.
FET switches S are each coupled between an end portion of a respective local bit line and a connection point P connecting the corresponding master bit line. Memory cells coupled to a particular local bit line are accessed by closing the corresponding switch S and opening the other switches in the corresponding column by appropriate control voltages on control lines 23.sub.1 -23.sub.4.
In general, bit line capacitance is proportional to bit line length. As such, bit line length is limited by the maximum bit line capacitance that can be tolerated. The maximum capacitance is generally determined by the allowable sensing margin and the power dissipation. With the hierarchical bit line architecture, the master bit line capacitance per unit length is less than the local bit line capacitance per unit length, since the local bit lines are directly coupled to the memory cells which significantly contribute to the local bit line capacitance, whereas the master bit lines are not directly coupled to the cells. Thus, for a given column length, the total capacitance can be significantly less than in a non-hierarchical layout (i.e., layouts with only one layer of bit lines, each extending the entire column length and directly coupled to the memory cells). Therefore, by using a hierarchical architecture, less space-consuming sense amplifiers are needed for a chip with a specific number of memory cells. That is, the architecture permits each sense amplifier to be used for more cells, coupled to the local bit lines and one long master bit line, thereby reducing the number of sense amplifiers per chip. A smaller chip size is thus possible, provided that the area allocated to the switches S and additional control circuitry does not exceed the area saved by reducing the number of sense amplifiers.
FIG. 2 illustrates a variation of the above-discussed hierarchical bit line architecture. The shown configuration will be referred to hereafter as a "hybrid" type hierarchical architecture. FIG. 2 shows the case in which only two local bit line pairs (LBL.sub.1, LBL.sub.1 ) and (LBL.sub.2, LBL.sub.2 ) are disposed on each side of an associated sense amplifier SA.sub.i. In each column C.sub.i of a memory cell subarray, the local bit lines nearest the sense amplifier, i.e., LBL.sub.1 and LBL.sub.1 , are connected to the drain or source of a respective switch 25.sub.1, with the other side of the switch connecting directly to the sense amplifier electronics at a circuit node 63. This circuit node 63 is generally the same circuit node that connects the sense amplifier electronics to the corresponding master bit line MBL or MBL. A switch 25.sub.2 is coupled between each far side local bit line LBL.sub.2 and LBL.sub.2 and the corresponding master bit line at a connection node d. Gaps g separate LBL.sub.1 from LBL.sub.2 and LBL.sub.1 from LBL.sub.2 . To access a memory cell MC coupled to LBL.sub.1 or LBL.sub.1 , switches 25.sub.1 are turned on (closed) while switches 25.sub.2 are off, and vice versa to access cells coupled to the far side local bit lines LBL.sub.2 and LBL.sub.2 . Thus, memory cells coupled to the far side local bit lines are operatively coupled to the sense amplifier via the far side local bit line and the master bit line, whereas those cells coupled to the near side local bit line are coupled to the sense amplifier only via the near side local bit line. As such, the configuration of FIG. 2 is referred to as a hybrid. If more than two local bit line pairs are used on each side of the sense amplifier, then the path connecting the memory cells coupled to the near-side local bit lines LBL.sub.1 and LBL.sub.1 consists of only the local bit line whereas the paths connecting the sense amplifier to the other memory cells in the column consists of the master bit line in series with the respective local bit line.